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Synopsys and TSMC expand A14-certified EDA and multi-die enablement

2 companies named across 5 categories, one of 18 articles referencing Synopsys. Previous coverage: NVIDIA expands NVIDIA Agent Toolkit with PhysicsNeMo and CUDA-X libraries (Jul 2026).

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Synopsys and Taiwan Semiconductor Manufacturing Company (TSMC) outlined new work intended to support design schedules for next-generation AI, high-performance computing, and advanced semiconductor systems. The effort centers on certified electronic design automation flows, multiphysics-aware signoff methods, multi-die design support, and silicon-proven Interface and Foundation IP for advanced process and packaging technologies.

The update describes an effort to address design complexity while enabling adoption of TSMC process and advanced packaging technologies. It also references multiple TSMC process nodes and packaging environments, including A14 certification activities and enablement tied to specific packaging technologies.

Functionally, the organizations said they applied AI-powered EDA flows and multiphysics-aware signoff methodologies in their design processes. The release also points to multi-die design flows and unified environments for co-design and simulation, including simulation of integrated voltage regulators on TSMC CoWoS technology, and a photonic and electronic co-design flow for co-packaged optics.

Synopsys and TSMC reported A14 certification across digital and analog flows, along with enablement for agentic AI capabilities. They said Synopsys collaborated on device routing enablement on A14, used Custom Compiler with LLM-assisted analysis and Fusion Compiler for automation, and developed an agentic AI chiplet floorplan co-optimization flow using 3DIC Compiler. For multi-die and packaging work, they cited IVR co-design and simulation on CoWoS, co-packaged optics design on TSMC COUPE through an integrated photonic and electronic co-design flow, and UCIe-A silicon demonstrations and tape-outs, including 64G UCIe IP tape-outs on 2nm and 3nm. “As AI systems continue to grow in scale and complexity, customers require proven IP, intelligent design solutions, and advanced packaging methodologies that work together seamlessly,” Michael Buehler-Garcia, Senior Vice President at Synopsys, said. “Our collaboration with Open Innovation Platform® (OIP) ecosystem partners like Synopsys continues to meet the rapidly growing demands of AI and high-performance computing,” Aveek Sarkar, Director of the Ecosystem and Alliance Management Division at TSMC, said.

Forward-looking statements were not provided beyond the described enablement, certifications, and reported demonstrations and tape-out milestones.

Press release, provided by Cision on behalf of Synopsys. Read the original.