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Enterprise Technology Glossary

Definitions, concepts, acronyms, and terminology used across enterprise technology markets.

The Decision Insights Glossary provides definitions and explanations for technology terms, acronyms, products, architectures, standards, and industry concepts used throughout enterprise IT.

Entries are designed to help technology professionals, business leaders, researchers, and students quickly understand terminology spanning networking, cloud computing, cybersecurity, artificial intelligence, software development, infrastructure, observability, telecommunications, and related domains.

Use the search bar to find specific terms, concepts, acronyms, technologies, or industry terminology.

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  • Vulnerability Scanning

    Vulnerability scanning is an automated security assessment process that detects and reports known weaknesses in systems, networks, and applications, enabling enterprises to prioritize remediation, support compliance obligations, and maintain structured visibility into their technical security posture over time.

  • VXLAN

  • Wafer Dicing

    Wafer dicing is the semiconductor manufacturing process that separates a processed silicon wafer into individual dies or chips using saw, laser, or plasma singulation. It matters because dicing quality, yield, and throughput directly affect chip cost, reliability, and supply for enterprise systems.

  • Wafer Dicing Equipment

    Wafer dicing equipment is a class of semiconductor manufacturing tools that cut processed wafers into individual dies or chips, enabling packaging and assembly. It matters to enterprises because it affects yield, reliability, cost per chip, and semiconductor supply chain planning.

  • Wafer Fabrication

    Wafer fabrication is the semiconductor manufacturing process that builds integrated circuits on silicon or other wafers through repeated deposition, patterning, and etching steps in cleanrooms, which establishes the electrical, cost, and supply characteristics of chips used in enterprise infrastructure.

  • Wafer Fabrication Process

    Wafer fabrication process is the controlled sequence of microfabrication steps that build semiconductor devices on a wafer, forming the electrical and physical characteristics that determine chip performance, power use, cost structure, and reliability in enterprise and data center systems.

  • Wafer Foundry

    Wafer foundry is a contract semiconductor manufacturing facility that fabricates integrated circuits on wafers for external customers. It matters in enterprise contexts because its process technologies, capacity and geographic profile affect chip availability, performance characteristics, cost structures and supply-chain risk.

  • Wafer Inspection System

    Wafer inspection system is a semiconductor manufacturing tool that detects and classifies defects or process variations on silicon wafers during fabrication, providing structured data for yield management, process control, and quality assurance in advanced chip production environments.

  • Wafer-Level Packaging

    Wafer-level packaging (WLP) is a semiconductor packaging method that completes all package formation on the wafer before dicing, producing near-die-size packages with short interconnects and high input/output density that affect device performance, form factor, and power efficiency in enterprise hardware.

  • Wafer Packaging Line

    Wafer packaging line is an integrated semiconductor manufacturing line that performs wafer-level assembly, interconnection, protection, and test to convert processed wafers into finished or semi-finished integrated circuit packages, which affects device performance, reliability, yield, cost, and supply assurance for enterprise systems.

  • Wafer Probe Test

    Wafer probe test is a semiconductor manufacturing step in which automated equipment electrically tests each integrated circuit on a silicon wafer before dicing and packaging, enabling yield screening, binning, and early quality control for enterprise chip products and platforms.

  • Wafer-Scale Acceleration

    Wafer-scale acceleration is a hardware design approach that uses an entire silicon wafer as one integrated accelerator for compute-intensive workloads, relevant to enterprises that run large AI, analytics, or high-performance computing tasks requiring high on-chip parallelism and bandwidth.

  • Wafer-Scale Integration

    Wafer-scale integration is a semiconductor design and manufacturing method that implements a large compute system across an entire silicon wafer, rather than separate chips, which matters for enterprises evaluating high-density accelerators for AI, high-performance computing, and data center workloads.

  • Wafer-Scale Neuromorphic System

    Wafer-scale neuromorphic system is a brain-inspired computing platform that implements large spiking neural networks directly on an almost entire silicon wafer, providing event-driven, parallel processing for select AI and signal-processing workloads in data center, high-performance, or edge computing environments.

  • Wafer Yield

    Wafer yield is the percentage of functional semiconductor dies on a processed wafer and serves as a core metric for fabrication efficiency, cost per die, and supply planning in semiconductor manufacturing and enterprise hardware strategies.

  • Wafer Yield Analysis

    Wafer yield analysis is the systematic evaluation of semiconductor wafer test and inspection data to quantify die yield, isolate defect and process-related yield loss mechanisms, and guide process, equipment, and design adjustments in enterprise semiconductor manufacturing environments.

  • WAN Optimization

    WAN optimization is a set of methods and tools that improve application performance and bandwidth efficiency over wide area networks, which matters for enterprises that operate branch offices, centralized data centers, and cloud workloads over constrained or high-latency links.

  • WAN Optimization Gateway

    WAN optimization gateway is a network device or virtual appliance that applies deduplication, compression, protocol optimization, and traffic management to improve performance and bandwidth efficiency of data flows over enterprise wide area networks connecting branches, data centers, and cloud environments.

  • WAN Performance Accelerator

    WAN performance accelerator is a hardware, virtual, or cloud-based system that improves effective performance of wide area network traffic using optimization, caching, compression, and protocol controls, which helps enterprises support application service levels over constrained or high-latency WAN links.

  • Warehouse Robotics Controller

    Warehouse robotics controller is a coordinated control layer that manages and monitors robot fleets performing storage, retrieval, and material-handling tasks in warehouses, enabling integration with enterprise systems, enforcement of safety and security policies, and analysis of operational data for planning and maintenance.