SK hynix presents future DRAM technology roadmap at IEEE VLSI 2025

SK hynix participated in the IEEE VLSI Symposium 2025 held June 8-12 in Kyoto, Japan, where the company presented a new DRAM technology roadmap. The plan addresses the scaling limitations associated with current DRAM technologies by considering a shift to the 4F² VG platform, which is projected to enhance performance and integration.

During the event, Cha Seon Yong, Chief Technology Officer of SK hynix, delivered a plenary session titled “Driving Innovation in DRAM Technology: Towards a Sustainable Future.” He noted that improving performance and capacity has become increasingly challenging under existing technology frameworks.

In his address, Cha mentioned that SK hynix will adopt 4F² VG technology as it allows for a reduction in the cell area while enhancing speed and efficiency through a vertical gate configuration. Additionally, the company aims to utilize 3D DRAM technology, viewed as vital for the future of memory solutions. Cha indicated that while industry concerns exist regarding costs associated with stacking layers in 3D DRAM, ongoing technological advancements can address those challenges.

Cha emphasized the importance of continuous innovation and industry collaboration to overcome historical boundaries in DRAM technology, referencing past advancements that pushed limits lower than previously expected. The symposium ended with Joodong Park, vice president of the Next Gen DRAM team, presenting research on the effects of VG and wafer bonding technology on the electrical characteristics of DRAM.