SK hynix presents future DRAM technology roadmap at IEEE VLSI 2025

SK hynix recently shared plans for its upcoming DRAM technology during the IEEE VLSI Symposium 2025 held from June 8-12 in Kyoto, Japan. This roadmap focuses on addressing current scaling limitations by transitioning to the 4F² VG platform, which may accommodate enhanced performance and integration.

Presentation Highlights

During the symposium, SK hynix Chief Technology Officer Cha Seon Yong hosted a plenary session titled “Driving Innovation in DRAM Technology: Towards a Sustainable Future.” He pointed out that achieving improved performance and capacity is increasingly difficult under the existing technological frameworks.

Technological Advancements

Cha noted that adopting the 4F² VG architecture would decrease the cell area while increasing speed and efficiency, owing to its vertical gate structure. Furthermore, he outlined the company's commitment to developing 3D DRAM technology, which he considers crucial for future memory solutions. While he acknowledged cost concerns associated with 3D DRAM stacking, he expressed confidence that ongoing advancements in technology could resolve these issues.

Collaborative Innovation

Cha stressed the necessity for continuous innovation and collaboration across the industry to surpass historical limits in DRAM development. He referenced previous breakthroughs, which had previously been thought unachievable. The symposium concluded with Joodong Park, vice president of the Next Gen DRAM team, presenting findings on the influence of VG and wafer bonding technology on DRAM's electrical properties.

This blog signals a fact-based summary of SK hynix’s recent initiatives at the IEEE VLSI Symposium, showcasing their focus on future DRAM technology.