SEALSQ Corp to exhibit quantum-resistant hardware at Embedded World 2026

SEALSQ Corp said it would attend Embedded World 2026 in Nuremberg from March 10–12 to present developments related to device security and provisioning at the event.

Embedded World brought together thousands of professionals and served as a forum where attendees examined cybersecurity and quantum threats and reviewed secure hardware and device identity topics, according to the announcement.

The company described hardware it planned to display, including a QVault Trusted Platform Module (TPM) that provided hardware-isolated key storage, secure boot, device attestation and platform integrity verification, and a QS7001 secure RISC-V microcontroller platform that included a Hardware Root of Trust (HRoT), native Post-Quantum Cryptography (PQC) algorithms selected by NIST, secure boot, firmware authentication and update capabilities.

SEALSQ outlined Public Key Infrastructure (PKI) and trust services such as end-to-end hardware-anchored device identities, Zero-Touch Provisioning (ZTP), certificate lifecycle management, continuous attestation and secure over-the-air updates with stated integrations for AWS Internet of Things (IoT), Azure and Matter; it also described IC’Alps’s full-turnkey Application-Specific Integrated Circuit (ASIC) and SoC development services and named partners TSMC, Intel Foundry, X-Fab, ams-OSRAM and GlobalFoundries.

The announcement included a proof-of-concept with Lattice Semiconductor that combined a TPM and Field Programmable Gate Array (FPGA) into a single reference design to demonstrate PQC at the hardware level, with live demonstrations scheduled at Lattice’s Hall 4, Booth 528 and SEALSQ’s own presence listed as Hall 5, Booth 178, which was described as Formula One themed in connection with a partnership with the BWT Alpine Formula One Team.

The communication included forward-looking statements that were subject to risks and uncertainties and identified factors such as SEALSQ's ability to continue transactions with material parties, market demand and semiconductor industry conditions, and the risks described in reports filed by SEALSQ with the Scope 1–3 Emission Calculator (SEC).