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SEALSQ Corp presented QS7001 for CNSA 2.0 compliance

Source Decision Insights Record Published February 11, 2026 Companies 2
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2 companies named across 6 categories, one of 70 articles referencing SEALSQ. Previous coverage: SEALSQ Corp presents root-to-quantum security platform (Feb 2026).

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C Level / Executive Team
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Chief Information Security Officer
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Security Architect
Buyer role
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Information Technology / Semiconductors & Semiconductor Equipment / Semiconductors

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SEALSQ Corp presented the QS7001 microcontroller at Tech&Fest and framed the device as a means to address new cryptographic transition requirements such as CNSA 2.0.

The company showcased the QS7001 last week in Grenoble and outlined that the chip could be embedded inside robots, autonomous systems, automotive ECUs, industrial controllers, Internet of Things (IoT) edge nodes, and other intelligent devices to comply with emerging post-quantum mandates and regulation like CNSA 2.0 or CRA.

The QS7001 combined a 32-bit RISC-V core with a dedicated cryptographic acceleration subsystem and implemented SHA-3 lattice-based post-quantum primitives in silicon, which reduced cycle count, memory footprint, and power consumption while mitigating timing and side-channel leakage risks. At Read-Only Memory (ROM) level it integrated a lattice-math accelerator optimized for Number Theoretic Transform operations, polynomial multiplication over module lattices, rejection sampling, modular reduction, and constant-time arithmetic, and the device achieves up to 10x performance improvement versus software-only Post-Quantum Cryptography (PQC) stacks.

The chip provided native hardware support for ML-DSA-87 (Dilithium 5) for firmware signing, ML-KEM (Kyber) for key establishment, SHA-3 hashing engines, AES-256 symmetric encryption, and a True Random Number Generator, and it included 512 KB embedded flash and secure SRAM partitions to support SKS, firmware image storage, encrypted bootloaders, and trusted execution environments. Security mechanisms comprised secure boot with anti-rollback, side-channel hardened cryptographic engines, active tamper detection sensors, voltage, frequency and glitch monitoring, secure key zeroization on tamper events, and memory protection units, with design pathways toward Common Criteria EAL5+ and Federal Information Processing Standard (FIPS) certification.

The communication included forward-looking statements regarding SEALSQ Corp and its businesses and said actual results may differ from those statements.

Press release, provided by Globe Newswire on behalf of SEALSQ. Read the original.

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