Verible

Verible is an open-source SystemVerilog developer tooling suite (hardware design and verification tooling) focused on parsing, formatting, linting, and analyzing Hardware Description Language (HDL) code to support design and verification workflows.

• SystemVerilog parser and front-end library (hardware design tooling)
• Code formatter for SystemVerilog source files (developer productivity tooling)
• Linter for style and structural checks on SystemVerilog code (code quality and compliance tooling)
• Language server and editor integration support for SystemVerilog (developer experience tooling)
• Utilities for syntax tree analysis, project-wide querying, and refactoring workflows (program analysis tooling)

More About Verible

Verible is an open-source suite of SystemVerilog developer tools (hardware design and verification tooling) under CHIPS Alliance, designed to parse, analyze, and transform SystemVerilog code used in hardware description and verification environments. It targets design and verification teams that maintain large hardware codebases and need automated support for formatting, linting, and structured analysis of SystemVerilog sources.

The core of Verible is a SystemVerilog parser and front-end library (program analysis tooling) that builds concrete and abstract syntax trees from SystemVerilog source files. This parsing capability underpins the project’s other tools, including the formatter, linter, and analysis utilities. The parser is designed to accept the SystemVerilog language as used in practical design and verification projects and to expose structured representations that other tools or integrations can consume.

Verible includes a SystemVerilog code formatter (developer productivity tooling) that enforces consistent layout and whitespace rules across a codebase. This tool operates on the parsed representation of the source and outputs formatted code according to defined style rules and configuration options. Teams can use the formatter in Continuous Integration (CI) pipelines, automated presubmit checks, or local developer workflows to maintain uniform style.

The project also provides a SystemVerilog linter (code quality and compliance tooling) that applies a set of style, readability, and structural rules to source files. The linter reports rule violations with locations and rule identifiers, and rules can typically be enabled, disabled, or configured. This supports code review workflows, automated gatekeeping in version control systems, and enforcement of organization-specific coding guidelines for hardware design and verification code.

Beyond formatting and linting, Verible exposes utilities for working with syntax trees and tokens (program analysis tooling). These tools support queries over parsed structures, pattern-based analysis, and assist with refactoring or migration tasks across multiple files. Because Verible is implemented as a collection of libraries and command-line tools, it can be integrated into custom flows, build systems, and analysis pipelines in enterprise environments.

Verible also includes support components for editor and language server integrations (developer experience tooling), allowing SystemVerilog projects to plug into standard development environments. This enables features such as on-save formatting, inline diagnostics from lint rules, and navigation powered by the parser. In enterprise contexts, Verible fits into the broader category of hardware design and verification tooling, complementing simulators, synthesis tools, and verification frameworks by focusing on source-level analysis, style, and structural correctness of SystemVerilog code.