Skip to main content

OmniXtend

OmniXtend is an open specification and reference implementation for cache-coherent memory access over standard Ethernet (network fabric / interconnect).

  • Open cache-coherent protocol over Ethernet for load/store memory semantics (network protocol)
  • Hardware-oriented specification with reference Reinforcement Test Learning (RTL) and tools under CHIPS Alliance (hardware design ecosystem)
  • Enables sharing main memory across multiple nodes using coherent transactions (system architecture)
  • Targets integration with RISC-V and other coherent agents via standard interfaces (processor / SoC integration)
  • Community-governed development under CHIPS Alliance for interoperable, vendor-neutral fabrics (open hardware collaboration)

More About OmniXtend

OmniXtend is a project under CHIPS Alliance that defines a cache-coherent protocol for performing load/store memory operations across Ethernet-based networks. It focuses on extending coherent memory semantics beyond a single chip or board, enabling systems in which processors and accelerators access shared memory over a commodity Ethernet fabric. The project provides a protocol specification and reference implementations intended for hardware designers, system architects, and vendors who require coherent interconnect behavior across distributed components.

The OmniXtend protocol (network protocol) supports cache-coherent transactions such as reads, writes, and coherence messages that are transported over standard Ethernet links. By doing this, it allows nodes to participate in a shared coherence domain while communicating via widely available networking hardware. The design targets use cases where multiple processors, accelerators, or memory controllers need coherent access to the same memory regions without relying only on proprietary interconnects. OmniXtend is positioned in the category of cache-coherent interconnects and fabric protocols that operate over existing network infrastructure.

Reference implementations in the OmniXtend repository (hardware IP / RTL) provide example hardware blocks and tooling aligned with the protocol specification. These implementations are intended as starting points or building blocks for system-on-chip designs, Field Programmable Gate Array (FPGA) prototypes, and other hardware platforms that want to interface with an OmniXtend fabric. The project aligns with CHIPS Alliance objectives around open hardware IP, reproducible design flows, and shared infrastructure for SoC development. Its materials are structured for integration into broader open-source hardware toolchains and verification environments used in enterprise and research settings.

In enterprise or institutional environments, OmniXtend is relevant where distributed systems require coherent memory sharing between CPUs and accelerators, or between multiple boards and chassis connected via Ethernet. System designers can use the protocol to create architectures in which memory modules, compute nodes, and specialized accelerators interact as peers within a coherent fabric (system architecture). This enables configurations where memory resources are disaggregated from compute nodes yet remain accessible with cache-coherent semantics, using Ethernet switches and links as the underlying transport.

OmniXtend’s association with CHIPS Alliance places it within an ecosystem that includes open-source RISC-V cores and related infrastructure (open hardware ecosystem). The protocol is designed to connect to coherent agents, such as processor clusters, through standard on-chip interfaces, while using Ethernet as the off-chip medium. This combination of an open protocol specification, hardware reference designs, and community governance provides enterprises and institutions with a vendor-neutral option for designing and evaluating coherent fabrics over Ethernet.